Joel's Research

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Installing the St. George Internet Payment Gateway module for Ruby

I upgraded a virtual server from x86 to x86.64 and found that I needed to recompile the Ruby bindings for the St. George Internet Payment Gateway library. I have only a vague recollection of how I did this once before, many years ago.

Download the Linux API. Install swig.

cd webpaySWIG-3.3/swig/
swig -ruby webpay.i
cat > extconf.rb << EOF
require 'mkmf'
create_makefile('webpay')
EOF
ruby extconf.rb
make
make install # (even better: just copy webpay.so to your application's directory)

Now, install the shared library. I tried but failed to get this working from the application’s directory (probably due to library search paths). It was quicker to just stick it in /usr/lib/.

cp ../libwebpayclient.1.17.so.x86_64 /usr/lib/
cd /usr/lib
ln -s libwebpayclient.1.17.so.x86_64 libwebpayclient.so
ldconfig

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LaTeX in TextMate

The TextMate project view gets a bit cluttered with LaTeX intermediate files. Here’s an easy way to hide them:

Preferences -> Advanced -> Folder References -> File Pattern

I added the extensions highlighted in bold.

!(/\.(?!htaccess)[^/]*|\.(tmproj|o|pyc)|/Icon\r|/svn-commit(\.[2-9])?\.tmp|\.aux|\.bbl|\.synctex\.gz|\.blg|\.fdb_latexmk)$

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s3cmd bandwidth limit 2

Ignore that last post!

I have now forked s3cmd on GitHub and have hacked in a proper bandwidth limiting system for uploads.

Edit: it uses timedelta’s total_seconds() method, which isn’t present in Python versions before 2.7. I should fix it to use the crummier, manual method.

Edit 2: I’ve now done this.

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s3cmd bandwidth limit

I use s3cmd to automatically back up files to Amazon S3. Recently I’ve noticed that it is flooding my upload bandwidth and making my VPS unusably slow because it doesn’t implement any bandwidth limiting options.

I haven’t been bothered to implement a complete rate limiting system, but there is one easy hack based on the built-in throttling system. Normally this only kicks in when a transfer fails, but you can hard-code a value in by modifying S3/S3.py:

def send_file(self, request, file, labels, throttle = 0, retries = _max_retries, offset = 0, chunk_size = -1):

I set throttle to 0.1 and upload speed seems to have settled at about 39 KB/s, which is perfectly acceptable for a background transfer of a big file that I’m in no particular hurry to upload.

It should be very easy to make a proper limiting. I had a look how wget implements this - essentially, it calculates the amount of time it would take to download a chunk at the specified speed, and sleeps to make up the difference.

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SSD installation!

I’ve entered the 21st century and replaced the hard drive in my late 2009 27” iMac with a 240GB OCZ Vertex 3 SSD. Changing the drive took about twenty minutes. Trying to get all of the dust out of the iMac’s screen took about an hour and a half and ultimately failed. In the end, it didn’t really matter - I can’t see them during normal operation!

Bootup when reopening all windows is very snappy (after a crash while I was in the middle of some work, this was what annoyed me enough to invest in an SSD) but during normal operation I haven’t noticed any huge benefits - perhaps I’m not doing enough real work :(

The other problem I had was that my Parallels Windows 7 virtual machine began blue screening and wouldn’t boot at all. In the end I had to reinstall it and my applications from scratch.

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ADRF6850 PLL parameter spreadsheet

I’ve made some adjustments to my ADRF6850 PLL parameter spreadsheet, after some poor datasheet reading caused me to miscalculate a CR10 value. The spreadsheet now calculates the correct CR10 (Reference Frequency Control) value.

I’ve only got a working version for Apple Numbers - I tried opening it in Excel earlier and it didn’t work, but didn’t bother figuring out why. If anyone is actually interested, I’d be happy to fix it.

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Slow debugging process

It took quite a lot of pain, but I’ve managed to get all four RF chips initialising! There were several problems, or perhaps only two. The four chips each have their own linear regulator, the MCP1725, but this was outputting a very low voltage. The four regulators have a shared shutdown control signal, which seemed to be floating at 1.1 V, and the PIC controlling the shutdown signal either didn’t have the drive strength to control it or couldn’t due to a soldering problem that I couldn’t spot. Solution? Set the PIC pin as an input and tie the control signal high.

One of the regulators was bad, cycling on and off at about 2 Hz, so I replaced it, which fixed it.

One of the RF chips might have been bad, but now I can’t be sure if the problem was with it or the bad regulator all along. I’ve put it aside and will try it on my next board.

All in all, a frustrating few days! Now I can get on with some quick and simple RF tests (which will also let me check the channel synchronisation, which I suspect I’ll need to correct for later), and then test the ADC.

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It took some intense rework, but the DDS works! It&#8217;s now outputting a nice 50&#160;MHz clock to the ADC.
I&#8217;ve decided that I really don&#8217;t like TQFP parts - especially when they have a thermal pad. It doesn&#8217;t help that I got the footprint wrong, so the chip doesn&#8217;t exactly self-align properly. Even when it was in the right spot, I almost always ended up with solder bridges between two pins, but beneath the pins where it was very difficult to see or fix.
After about a dozen attempts to re-set the chip, and destroying one AD9952 after its AVDD regulator went from 1.8 to 3.56&#160;V (possibly after the ground lead fell off), it now works properly. I&#8217;d like to analyse the phase noise of the DDS using one of my spectrum analysers but don&#8217;t have a good way to probe it without loading the circuit - I&#8217;ll have to think about this a bit.
The next steps will be to:
Check that the ADC is working correctly, using my existing capture code.
Bring up and test the RF front end hardware.
Test the signal chain from end (RF) to end (Ethernet).
Revisit the OCXO disciplining firmware, though this isn&#8217;t really critical at this stage.

It took some intense rework, but the DDS works! It’s now outputting a nice 50 MHz clock to the ADC.

I’ve decided that I really don’t like TQFP parts - especially when they have a thermal pad. It doesn’t help that I got the footprint wrong, so the chip doesn’t exactly self-align properly. Even when it was in the right spot, I almost always ended up with solder bridges between two pins, but beneath the pins where it was very difficult to see or fix.

After about a dozen attempts to re-set the chip, and destroying one AD9952 after its AVDD regulator went from 1.8 to 3.56 V (possibly after the ground lead fell off), it now works properly. I’d like to analyse the phase noise of the DDS using one of my spectrum analysers but don’t have a good way to probe it without loading the circuit - I’ll have to think about this a bit.

The next steps will be to:

  • Check that the ADC is working correctly, using my existing capture code.
  • Bring up and test the RF front end hardware.
  • Test the signal chain from end (RF) to end (Ethernet).
  • Revisit the OCXO disciplining firmware, though this isn’t really critical at this stage.

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MPLAB X - first thoughts

I foolishly used a PIC18F24K22 on my receiver board, possibly because it has a good compromise of large flash size, two MSSP controllers, low price, and availability from element14. It turns out my PICkit 2 can only program and not debug with this part. I spent a good few hours stuck on a problem with getting SPI to work, so I broke down and ordered a PICkit 3 for just under $50, which arrived the following morning.

It turned out that the SPI problem was a very stupid typo that I fixed in the meantime - I was setting SSPXCON1 to 0b0010000, which is most definitely not eight bits, so the ‘enable SPI’ flag was not being set at all.

Anyway, PICkit 3 is well supported by MPLAB X, which runs on Mac OS X! I installed it and after a bit of fiddling around (the MPLAB X download page gives you older versions of HI-TECH C that don’t support the PIC18F24K22), was up and running. First impressions are that it is loads better than the old MPLAB. The editor sucks a whole lot less and has SCM support. Best of all, I don’t need to run Windows XP in VMWare any longer (PICkit 2 didn’t work well with Parallels).

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LCD works! The fact that I haven&#8217;t finished this RF power meter project has been niggling me for a very long time, so I spent a few hours on a Sunday evening working on it. All of this was spent trying to get the LCD going, though!
It wasn&#8217;t too difficult (though I felt envious that Arduino users have a complete HD44780 library built in), but I made a silly mistake in the code early on and it took me quite a long time to find it. I also discovered that I&#8217;d connected the wrong four LCD pins for the 4-bit interface.
Next steps: get the ADC working and displaying values.

LCD works! The fact that I haven’t finished this RF power meter project has been niggling me for a very long time, so I spent a few hours on a Sunday evening working on it. All of this was spent trying to get the LCD going, though!

It wasn’t too difficult (though I felt envious that Arduino users have a complete HD44780 library built in), but I made a silly mistake in the code early on and it took me quite a long time to find it. I also discovered that I’d connected the wrong four LCD pins for the 4-bit interface.

Next steps: get the ADC working and displaying values.